1. Field of the Invention
The invention pertains to the field of disk drive controllers. More particularly, the present invention pertains to disk drive microcontrollers, read only program code memory and the interface therebetween.
2. Description of the Related Art
If the speed at which a microcontroller executes program code words is matched by the speed at which the memory storing these program code words is able to provide them, then the microcontroller and code memory are evenly matched. Under such a state, the microcontroller requests a program code word from the code memory by supplying the code memory with the address of the program code word requested. The code memory then decodes the address and supplies the microcontroller with the program code word located at the address supplied by the microcontroller as soon as the microcontroller is able to process it.
However, a problem arises when the microcontroller processes instruction code words faster than the code memory is able to supply them. The speed of the code memory then becomes a bottleneck, limiting the rate at which the microcontroller processes instructions to the rate at which the code memory is able to supply the program code words. Under these circumstances, the microcontroller is forced to wait in an idle state for code words to appear on its data bus from the slower code memory, without executing any instructions. The clock cycles during which the microcontroller waits for the slower code memory to place requested program code words on the data bus are appropriately called wait states.
It has become apparent that the speed of microcontrollers has outpaced the speed of read only memories, the type of memory typically used to store program code words. A number of palliative measures have been adopted to attempt to address this disparity in operating speeds. One such measure is simply to insert a predetermined number of wait states, during which the microcontroller is idle, waiting for a next program code word to be placed on its data bus from the read only memory. This is, however, a less than optimal solution, as microcontroller resources are not efficiently utilized.
Another measure that has been proposed divides the code memory into two banks of memories; namely, one memory bank for storing code words whose addresses are odd and another memory bank for storing code words whose addresses are even. This is commonly called interleaved memory. Using interleaved even and odd memories, Yamada, in U.S. Pat. No. 5,594,888, speeds up read operations of a program stored in a ROM by simultaneously latching an odd byte and the next consecutive even byte (or vice-versa) of a multi-byte instruction word from the odd and even memory banks, respectively, responsive to two read signals. However, such an approach appears limited to retrieving consecutive bytes of a single multi-byte instruction and appears to require the re-generation of a code word address for each new instruction. Moreover, this approach requires complex signaling, additional signal pins on the device and yields only an incremental improvement in microcontroller utilization, and then only for multi-byte instructions. The problem of how to efficiently supply code words from a slow code memory to a relatively faster microcontroller remains unsolved.
What is needed, therefore, is a means for efficiently supplying program code words from a slow code memory to a relatively faster microcontroller. In particular, what is needed is a means for supplying a microcontroller with the requisite program code words from a relatively slower code memory that does not require the microcontroller to generate addresses for linear code.